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[Applications] pci_core

Description: PCI logicore,在某网站上下载的ip核文件，希望具有参考价值，
Platform: | Size: 91245 | Author: 王林 | Hits:

[Other resource] or1k[1].tar

Description: 好东西啊,PCI的IP核.大家快下吧.@可以用来参考.FPGA设计的
Platform: | Size: 1132295 | Author: chen qiming | Hits:

[Other resource] Pcit32vhdl

Description: PCI 32 target IP for Fpga/asic Designer
Platform: | Size: 428389 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] ml505_pcie_x1_plus

Description: Xilinx 公司PCI Express IP核应用参考设计。通过这个样例，用户可以掌握PCI Express应用设计的一般方法，了解PCI Express的工作原理。-Xilinx Inc. PCI Express IP core reference design applications. Through this example, the user can master the application of the design of PCI Express general approach to understand the working principle of PCI Express.
Platform: | Size: 1798144 | Author: daniel J | Hits:

[VHDL-FPGA-Verilog] CPRI

Description:
Platform: | Size: 933888 | Author: 郭坚 | Hits:

[VHDL-FPGA-Verilog] pci_core

Description: pci CORES 从外国网站上弄下来的，大家可以看看啊-pci CORES from foreign web sites get down, we will look at ah
Platform: | Size: 28672 | Author: haitao | Hits:

[VHDL-FPGA-Verilog] pci_arbi_quicklogic

Description: pci总线仲裁ip，对学习者有很高的参考价值。-pci bus arbitration ip, on the learners have a high reference value.
Platform: | Size: 3072 | Author: 王廷龙 | Hits:

[VHDL-FPGA-Verilog] hgb_pci_host

Description: 内有一PCI 主 和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持： 1、 对目标PCI_T进行配置； 2、 对目标进行单周期读写； 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
Platform: | Size: 2712576 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA_8008

Description: pci pci转local bus总线的应用，使用IPcore alter器件-pci pci convert local bus application,use alter IP core
Platform: | Size: 493568 | Author: robincyh | Hits:

[VHDL-FPGA-Verilog] 1

Description: 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
Platform: | Size: 2646016 | Author: likufan | Hits:

[VHDL-FPGA-Verilog] pci_32tlite_oc

Description: 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
Platform: | Size: 3941376 | Author: 陈达燕 | Hits:

[VHDL-FPGA-Verilog] IPcore

Description: 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
Platform: | Size: 903168 | Author: 李同滨 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA应用开发入门与典型实例 代码 FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。 -FPGA Application Development and Typical examples of code for FPGA (field programmable logic device) for its small size, low power consumption, high stability, the advantages are widely used in the design of electronic products. This book comprehensively explained the background FPGA system design, hardware design, hardware description language Verilog HDL syntax and basic common statement, FPGA use of the software development tools, FPGA-based soft-core embedded systems, FPGA design of the basic principles , skills, IP core, FPGA interface design field in a typical application, FPGA+ DSP system design and debug, and digital zoom systems and PCI data acquisition system design of two cases of complete system.
Platform: | Size: 10980352 | Author: 海到无涯 | Hits:

[VHDL-FPGA-Verilog] fs10_mt64

Description: pci ip核pci_mt64的数据库资料-pci data
Platform: | Size: 160768 | Author: 小燕 | Hits:

[Software Engineering] CPCI_PCIbus

Description: 为构建一个紧凑、灵活的 CPC I系统,在 IP核的基础上,采用 FPGA来实现 PCI总线接口电路。-To construct a compact and flex ible CPC I syste m, the PCI i nte rface c i rcuit i s i mp l em ented by FPGA based on IP core。
Platform: | Size: 335872 | Author: houyongchang | Hits:

[Software Engineering] DesignCPCIanalogonFPGA

Description: 本文实现了8通道的12位D/A模拟输出板卡的设计。该设计是基于FPGA的3U CPCI板卡，可以提供8通道的模拟电压和电流输出，各路电压输出范围可以配置成0~5V、0~10V、-5~5V或-10V~10V，各路输出电流可以配置成4~20mA、0~20mA或0~24mA。本设计摒弃了常规的CPCI接口芯片，采用FPGA十PCI IP CORE的设计方案，大幅度提高了系统的集成度和调试速度，缩短了系统的开发周期。方案使用专门的WDM (windows driver model)开发工具Driver Studio，成功实现了内核模式驱动开发的设计目标。-This realization of the 8-channel 12-bit D/A analog output board design. The design is FPGA-based 3U CPCI board, provides 8 channels of analog voltage and current output, and the brightest output voltage range can be configured as 0 ~ 5V, 0 ~ 10V,-5 ~ 5V or-10V ~ 10V, the brightest output current can be configured as 4 ~ 20mA, 0 ~ 20mA or 0 ~ 24mA. The design abandoned the conventional CPCI interface chip, an FPGA ten PCI IP CORE design, greatly improving system integration and debugging speed, shorten system development cycle. Program using a special WDM (windows driver model) development tool Driver Studio, successfully developed a kernel-mode driver design goals.
Platform: | Size: 130048 | Author: 反对撒 | Hits:

[VHDL-FPGA-Verilog] Xilinx_PCI_Express_IP_project

Description: Xilinx公司PCI Express IP核应用参考设计
Platform: | Size: 1658880 | Author: cxl | Hits:

[VHDL-FPGA-Verilog] Ms32pci

Description: PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL! Author is Ovidiu Lupas! MASTER model generates PCI compliant signals checks Target signal compliance with PCI checks data received from Target for correctness generates assertion reports if Target signals are not PCI compliant TARGET model generates PCI compliant signals checks Master signal compliance with PCI checks data received from Master for correctness generates assertion reports if Master signals are not PCI compliant Description The models are boardlevel simulation models and are useful in the testing phase of the PCI cores design. The models are 32 bit, 33 MHz PCI compliant but are easy upgradable to 64 bit, 66 MHz. The models are free you can redistribute them and/or modify them under the terms of the GNU General Public License as published by the Free Software Foundation either version 2 of the License, or (at your option) any later version. The models are distributed in the hope that they will be useful, but WITH
Platform: | Size: 6144 | Author: kity | Hits:

[VHDL-FPGA-Verilog] PCIIP-core

Description: 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generation. It also generates read and write allow signals, which are used for enabling/disabling memory used for FIFO. Control logic can be used for independent read and write clocks.
Platform: | Size: 1946624 | Author: chen | Hits:

[Other] pci-compiler-user-guide

Description: 基于IP核的CPCI总线的设计与实现,CPCI总线设计应用手册，32位CPCI总线应用手册-Design and implementation of CPCI bus-based IP core, CPCI bus design application notes, 32-bit CPCI bus Application Notes
Platform: | Size: 2395136 | Author: 田雨 | Hits:
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